INTEL 8051 MICROCONTROLLER

The Intel 8051 is a Harvard architecture, single chip microcontroller (µC) which was developed by Intelin 1980 for use in embedded systems. Intel's original versions were popular in the 1980s and early 1990s, but has today largely been superseded by a vast range of faster and/or functionally enhanced 8051-compatible devices manufactured by more than 20 independent manufacturers including Atmel,Infineon Technologies (formerly Siemens AG), Maxim Integrated Products (via its Dallas Semiconductorsubsidiary), NXP (formerly Philips Semiconductor), Nuvoton (formerly Winbond), ST Microelectronics,Silicon Laboratories (formerly Cygnal), Texas Instruments and Cypress Semiconductor. Intel's official designation for the 8051 family of µCs is MCS 51.

Intel's original 8051 family was developed using NMOS technology, but later versions, identified by a letter C in their name (e.g., 80C51) used CMOS technology and were less power-hungry than their NMOS predecessors. This made them more suitable for battery-powered devices.

Contents [hide] 1 Important features and applications 2 Programming 3 Instruction set 4 Related processors 5 References 6 External links

[edit]Important features and applications

i8051 microarchitecture.

• It provides many functions (CPU, RAM, ROM, I/O, interrupt logic, timer, etc.) in a single package
• 8-bit ALU, Accumulator and Registers; hence it is an 8-bit microcontroller
• 8-bit data bus - It can access 8 bits of data in one operation
• 16-bit address bus - It can access 2¹⁶ memory locations - 64 kiB (65536 locations) each of RAM and ROM
• On-chip RAM - 128 bytes (data memory)
• On-chip ROM - 4 kiB (program memory)
• Four byte bi-directional input/output port
• UART (serial port)
• Two 16-bit Counter/timers
• Two-level interrupt priority
• Power saving mode

A particularly useful feature of the 8051 core is the inclusion of a boolean processing engine which allows bit-level boolean logic operations to be carried out directly and efficiently on internal registers and RAM. This feature helped to cement the 8051's popularity in industrial control applications. Another valued feature is that it has four separate register sets, which can be used to greatly reduce interrupt latency compared to the more common method of storing interrupt context on a stack.

The 8051 UARTs make it simple to use the chip as a serial communications interface. External pins can be configured to connect to internal shift registers in a variety of ways, and the internal timers can also be used, allowing serial communications in a number of modes, both synchronous and asynchronous. Some modes allow communications with no external components. A mode compatible with an RS-485 multi-point communications environment is achievable, but the 8051's real strength is fitting in with existing ad-hoc protocols (e.g., when controlling serial-controlled devices).

Once a UART, and a timer if necessary, have been configured, the programmer needs only to write a simple interrupt routine to refill thesend shift register whenever the last bit is shifted out by the UART and/or empty the full receive shift register (copy the data somewhere else). The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks.

8051 based microcontrollers typically include one or two UARTs, two or three timers, 128 or 256 bytes of internal data RAM (16 bytes of which are bit-addressable), up to 128 bytes of I/O, 512 bytes to 64 kB of internal program memory, and sometimes a quantity of extended data RAM (ERAM) located in the external data space. The original 8051 core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. With a 12 MHz clock frequency, the 8051 could thus execute 1 million one-cycle instructions per second or 500,000 two-cycle instructions per second. Enhanced 8051 cores are now commonly used which run at six, four, two, or even one clock per machine cycle, and have clock frequencies of up to 100 MHz, and are thus capable of an even greater number of instructions per second. All SILabs, some Dallas and a few Atmel devices have single cycle cores.

Even higher speed single cycle 8051 cores, in the range 130 MHz to 150 MHz, are now available in internet downloadable form for use inprogrammable logic devices such as FPGAs, and at many hundreds of MHz in ASICs, for example the netlist from www.e8051.com. Top clock speed 8051 cores reach over 200 MHz in today's FPGA technologies - as an example www.dcd.pl.

Common features included in modern 8051 based microcontrollers include built-in reset timers with brown-out detection, on-chip oscillators, self-programmable Flash ROM program memory, bootloader code in ROM, EEPROM non-volatile data storage, I²C, SPI, and USB host interfaces, CAN or LIN bus, PWM generators, analog comparators, A/D and D/A converters, RTCs, extra counters and timers, in-circuit debugging facilities, more interrupt sources, and extra power saving modes.

[edit]Programming

There are various high level language compilers for 8051. Several C compilers are available for the 8051, most of which feature extensions that allow the programmer to specify where each variable should be stored in its six types of memory, and provide access to 8051 specific hardware features such as the multiple register banks and bit manipulation instructions. There are many commercial C compilers. SDCC is a popular open source C compiler. Other high level languages such as Forth, BASIC, Pascal/Object Pascal, PL/M and Modula 2 are available for the 8051, but they are less widely used than C and assembly.

[edit]Instruction set

Arithmetic Operations

Mnemonic	Description	Bytes	Cycles
ADD A,Rn	Add register to A	1	1
ADD A,direct	Add direct byte to A	2	1
ADD A,@Ri	Add indirect RAM to A	1	1
ADD A,#data	Add immediate data to A	2	1
ADDC A,Rn	Add register to A with Carry	1	1
ADDC A,direct	Add direct byte to A with Carry	2	1
ADDC A,@Ri	Add indirect RAM to A with Carry	1	1
ADDC A,#data	Add immediate data to A with Carry	2	1
SUBB A,Rn	Subtract register from A with Borrow	1	1
SUBB A,direct	Subtract direct byte from A with Borrow	2	1
SUBB A,@Ri	Subtract indirect RAM from A with Borrow	1	1
SUBB A,#data	Subtract immediate data from A with Borrow	2	1
INC A	Increment A	1	1
INC Rn	Increment register	1	1
INC direct	Increment direct byte	2	1
INC @Ri	Increment indirect RAM	1	1
DEC A	Decrement A	1	1
DEC Rn	Decrement register	1	1
DEC direct	Decrement direct byte	2	1
DEC @Ri	Decrement indirect RAM	1	1
INC DPTR	Increment Data Pointer	1	2
MUL AB	Multiply A and B (A x B => BA)	1	4
DIV AB	Divide A by B (A/B => A + B)	1	4
DA A	Decimal Adjust A	1	1

Logical Operations

Mnemonic	Description	Bytes	Cycles
ANL A,Rn	AND register to A	1	1
ANL A,direct	AND direct byte to A	2	1
ANL A,@Ri	AND indirect RAM to A	1	1
ANL A,#data	AND immediate data to A	2	1
ANL direct,A	AND A to direct byte	2	1
ANL direct,#data	AND immediate data to direct byte	3	2
ORL A,Rn	OR register to A	1	1
ORL A,direct	OR direct byte to A	2	1
ORL A,@Ri	OR indirect RAM to A	1	1
ORL A,#data	OR immediate data to A	2	1
ORL direct,A	OR A to direct byte	2	1
ORL direct,#data	OR immediate data to direct byte	3	2
XRL A,Rn	Exclusive-OR register to A	1	1
XRL A,direct	Exclusive-OR direct byte to A	2	1
XRL A,@Ri	Exclusive-OR indirect RAM to A	1	1
XRL A,#data	Exclusive-OR immediate data to A	2	1
XRL direct A	Exclusive-OR A to direct byte	2	1
XRL direct,#data	Exclusive-OR immediate data to direct byte	3	2
CLR A	Clear A	1	1
CPL A	Complement A	1	1
RL A	Rotate A Left	1	1
RLC A	Rotate A Left through Carry	1	1
RR A	Rotate A Right	1	1
RRC A	Rotate A Right through Carry	1	1
SWAP A	Swap nibbles within A	1	1

Data Transfer Operations

Mnemonic	Description	Bytes	Cycles
MOV A,Rn	Move register to A	1	1
MOV A,direct	Move direct byte to A	2	1
MOV A,@Ri	Move indirect RAM to A	1	1
MOV A,#data	Move immediate data to A	2	1
MOV Rn,A	Move A to register	1	1
MOV Rn,direct	Move direct byte to register	2	2
MOV Rn,#data	Move immediate data to register	2	1
MOV direct,A	Move A to direct byte	2	1
MOV direct,Rn	Move register to direct byte	2	2
MOV direct,direct	Move direct byte to direct byte	3	2
MOV direct,@Ri	Move indirect RAM to direct byte	2	2
MOV direct,#data	Move immediate data to direct byte	3	2
MOV @Ri,A	Move A to indirect RAM	1	1
MOV @Ri,direct	Move direct byte to indirect RAM	2	2
MOV @Ri,#data	Move immediate data to indirect RAM	2	1
MOV DPTR,#data16	Load Data Pointer with 16-bit constant	3	1
MOVC A,@A+DPTR	Move Code byte relative to DPTR to A	1	2
MOVC A,@A+PC	Move Code byte relative to PC to A	1	2
MOVX A,@Ri	Move External RAM (8-bit addr) to A	1	2
MOVX A,@DPTR	Move External RAM (16-bit addr) to A	1	2
MOVX @Ri,A	Move A to External RAM (8-bit addr)	1	2
MOVX @DPTR	A Move A to External RAM (16-bit addr)	1	2
PUSH direct	Push direct byte onto stack	2	2
POP direct	Pop direct byte from stack	2	2
XCH A,Rn	Exchange register with A	1	1
XCH A,direct	Exchange direct byte with A	2	1
XCH A,@Ri	Exchange indirect RAM with A	1	1
XCHD A,@Ri	Exchange low-order Digit indirect RAM with A	1	1

Single Bit (Boolean Variable) Operations

Mnemonic	Description	Bytes	Cycles
CLR C	Clear Carry flag	1	1
CLR bit	Clear direct bit	2	1
SETB C	Set Carry flag	1	1
SETB bit	Set direct bit	2	1
CPL C	Complement Carry flag	1	1
CPL bit	Complement direct bit	2	1
ANL C,bit	AND direct bit to Carry flag	2	2
ANL C,/bit	AND complement of direct bit to Carry flag	2	2
ORL C,bit	OR direct bit to Carry flag	2	2
ORL C,/bit	OR complement of direct bit to Carry flag	2	2
MOV C,bit	Move direct bit to Carry flag	2	1
MOV bit,C	Move Carry flag to direct bit	2	2

Program Flow Control

Mnemonic	Description	Bytes	Cycles
ACALL addr11	Absolute subroutine call	2	2
LCALL addr16	Long subroutine call	3	2
RET	Return from subroutine	1	2
RETI	Return from interrupt	1	2
AJMP addr11	Absolute Jump	2	2
LJMP addr16	Long Jump	3	2
SJMP rel	Short Jump at relative address	2	2
JMP @A+DPTR	Jump indirect relative to DPTR	1	2
JZ rel	Jump if A is Zero	2	2
JNZ rel	Jump if A is Not Zero	2	2
JC rel	Jump if Carry flag is set	2	2
JNC rel	Jump if No Carry flag	2	2
JB bit,rel	Jump if direct Bit is set	3	2
JNB bit,rel	Jump if direct Bit is Not set	3	2
JBC bit,rel	Jump if direct Bit is set and Clear bit	3	2
CJNE A,direct,rel	Compare direct to A and Jump if Not Equal	3	2
CJNE A,#data,rel	Compare immediate to A and Jump if Not Equal	3	2
CJNE Rn,#data,rel	Compare immediate to register and Jump if Not Equal	3	2
CJNE @Ri,#data,rel	Compare immediate to indirect and Jump if Not Equal	3	2
DJNZ Rn,rel	Decrement register and Jump if Not Zero	2	2
DJNZ direct,rel	Decrement direct byte and Jump if Not Zero	3	2
NOP	No operation	1	1

Notes

Rn Working register R0-R7

direct 128 internal RAM locations, any I/O port, control or status register

@Ri Indirect internal RAM location addressed by register R0 or R1

1. data 8-bit constant included in instruction

1. 
   
2. data16 16-bit constant included in instruction

1. 
   

bit 128 software flags, any I/O pin, control or status bit

addr16 Destination address may be anywhere in 64-kByte program address space

addr11 Destination address will be within same 2-kByte page of program address space as first byte of the following instruction

rel 8-bit offset relative to first byte of following instruction (+127, -128)

All mnemonics copyrighted (C) Intel Corporation 1979